Avoiding Time Loss Due to EQs From the Fabricator
“Time waste differs from material waste in that there can be no salvage. The easiest of all wastes and the hardest to correct is the waste of time, because wasted time does not litter the floor like wasted material.” - Henry Ford -
As an assembler, we are asked to do a full turnkey build. We purchase the bare PCBs, the parts and do the assembly.
This frequently means when Engineering Questions (EQs) arise, we lose time communicating the questions from the fabricator to the end-user which causes delays.
Furthermore, we must wait for the acknowledgement response and approval from the end-user further causing a time -hit that needs to be recouped.
I can only stress how critical time is, and that good data saves time and delays.
“Human error causes 23% of unplanned downtime in manufacturing. That’s 2.5x higher than in other sectors.” (source)
In the following case study, customer notes vs. engineering questions from the board fabricator slowed the process down, resulting in lost build time.
What were the fabricator EQs (Engineering Questions) that slowed this build, effectively losing three full days of the build time?
Let's look at some things that create engineering questions from the fabricator and solve them by a simple review of the output package for Fabrication and Assembly.=
1st question from the fabricator:
"One of the stack-ups shows a 16-layer with impedance control, and one shows an 8-layer stack up. We need to make sure we are not missing layers. Should we disregard the 16-layer stack up and the Controlled impedances associated with it?"
After review, two separate stack-ups were in the output Fab dataset.
One: A 16-layer stack up. Presumably from a previous or preliminary build with numerous Impedance callouts and specific dielectrics to achieve the same.
The second: An 8-layer stack up. A quick look at the Gerber data provided shows just 8 layers.
How do you avoid time loss due to a question like this one?
A simple solution: Cull out any old information that is not relevant to the build at hand. A sound output package review process would have caught this and deleted the errant 16-layer stack up.
2nd EQ from the fabricator has to do with the Fab notes:
"The files do not contain IPC netlist files. Please either provide the IPC netlist file or approve standard electrical test based on your Gerber data and disregard note asking for a netlist-based test."
NOTE: The customer's fab drawing said, "Boards to be 100% tested for opens and shorts against supplied IPC-D-356A; certification of this test is required."
At this point, having been asked on numerous occasions to "Generate" a netlist file based on the Gerber data, I need to stress that that defeats the purpose of the IPC netlist compare.
Remember, "Generating" a netlist based on the Gerber data DOES NOT mean a comparison is made to the supplied IPC-Netlist. At NO point would generating a netlist file based on the raw image data find any opens or shorts if they already existed on the Gerber data.
The following EQ was also based on an incomplete or vague note on the fab drawing during the communication process.
Question # 3 from the fabricator read:
"The spec is unclear about which vias require filling and capping. Would you mind identifying which vias require this, if any?"
NOTE: The fab drawing says, "All vias are through-hole, include some via-in-pad are the be filled and capped."
The statement on the note leads us to ask more questions.
- Which vias are to be filled and capped?
If a cam operator has to "fish" out only true Via-in-pad, they may miss some. Additionally, references to "Filled and capped" begs the next question. What are they filled with? Epoxy? Silver -epoxy? Copper epoxy? Plated shut with copper? (to match the CTE of the board materials)
- For instance, if you have .008 vias that are both via-in-pad and elsewhere on the board, how does the cam operator at the fabricator find them all to edit them or add drill compensations?
Here, I have advised in the past that the end-user specify all the Via-in-pad by using a unique hole size. Something like .0081 or even .00801, these slight differences cannot be resolved by the fabricator but allow the cam operator to select them for drill compensation. This can be added to the note, the drill table, or even the "read-me." All would have precluded the question and response lost time.
What can we take away from this case study?
- First, make sure you have no extra or conflicting data in your output package.
(like two different stack up's)
- Second, make sure if you are asking for a specific type of test based on an IPC-356 netlist that you provide, said netlist, or re-write the note to indicate standard electrical test per IPC 9252B.
- And lastly, make sure the notes you have are not open for interpretation or ambiguous.
I cannot stress how important it is to thoroughly review your notes to avoid these types of EQs and the resulting time loss.
Thanks for reading.
About the Author
Mark Thompson C.I.D. - Sr. PCB technologist/ Engineering Manager
Mark has been in the engineering field for over 38 years. In 1993, he relocated to the Pacific Northwest, where he worked for Pacific Circuits, which became TTM, and Praegitzer Industries. He worked with Prototron from 1996–2019 and is now an engineering manager at Out of the Box Manufacturing.
He is passionate about his career, followed by aviation, art, and history. In his free time, Mark is an avid pilot, with a fondness for the aircraft of yesteryear. Mark says, "I have been privileged to fly many biplanes from the 1930s and 1940s, including Fleets, Stearmans, and N3Ns."
Mark enjoys sharing information and answering questions about PCB fabrication. Mark says: “The more information I can provide, the more fulfilled my customers and I will be.” Reach out to Mark here.